Design-Reuse

True Circuits Introduces New Line of Phase-Locked Loop Hard Macros; Significantly Smaller PLL Sizes Achieved Without Sacrificing Performance

LOS ALTOS, Calif.--(BUSINESS WIRE)--June 8, 2004-- True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics ...
EDN

System Applications with IDT’s Zero-Delay Buffers

This application report presents different methods of achieving a defined phase relationship between the input reference clock and output clock for IDT PLL-based zero-delay buffers. The report focuses ...
EDN

Achieve low PLL jitter via improved power integrity

A PLL (phase locked loop) or frequency synthesizer is used to generate high frequency clocks to ADCs and other devices. It is crucial to maintain a very low jitter or phase noise in the PLL output to ...
Electronic Design

Phase-Noise Modeling, Simulation, and Propagation in Phase-Locked Loops (Part 2)

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...
Design-Reuse

Fully Digital Implemented Phase Locked Loop

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...
Hackaday

Unlock The Phase Locked Loop

If you want a stable oscillator, you usually think of using a crystal. The piezoelectric qualities of quartz means that it can be cut in a particular way that it will oscillate at a very precise ...
Electronics Weekly

Phase-locked loop triumph

I have always had a soft spot for phase-locked loops – at least, I have since I first found out what they were. What I like about them is that they servo into the best answer for a given situation – ...